DESKTOP-PUHFO60\dsx2016
ee2ca3edfc
Leave 2.8 wiring unchanged; release GT911 INT after reset so SCL21 can share CN1. Co-authored-by: Cursor <cursoragent@cursor.com>
18 lines
608 B
Plaintext
18 lines
608 B
Plaintext
name: CYD sgp30test (cyd_35r)
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git: 1b2fe27
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date: 2026-10-25
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board: ESP32-3248S035 (ST7796 + GT911)
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sgp30: SDA=GPIO22 SCL=GPIO21
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tft_bl: GPIO27
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flash_size: 4MB
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offsets:
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0x1000 bootloader.bin
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0x8000 partitions.bin
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0xe000 boot_app0.bin
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0x10000 firmware.bin
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sha256:
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bootloader.bin 3D234A7471F67B013686DABD4DEE7C1FA915C9928463616A94BC9297ACF1ABF8
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boot_app0.bin F94C5D786A7A8FAB06AC5D10E33BF37711A6697636DC037559EA19CC410A17F0
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firmware.bin 35AD57B34071317C3B1D3CF25B7F9E41C780D9134577A7229A113E8936BA3040
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partitions.bin 0A8B5720E7B77FF11F1462458C3A509DEE79224E5279898F26D6A2E3AE0517B7
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