DESKTOP-PUHFO60\dsx2016 ee2ca3edfc Align 3.5C pins with CYD_PROJECT_GUIDE: TFT_BL=27, SGP30 SDA22/SCL21. ...

Leave 2.8 wiring unchanged; release GT911 INT after reset so SCL21 can share CN1.

Co-authored-by: Cursor <cursoragent@cursor.com>

2026-10-25 10:53:33 +08:00

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media

Align 3.5C pins with CYD_PROJECT_GUIDE: TFT_BL=27, SGP30 SDA22/SCL21.

2026-10-25 10:53:33 +08:00

boot_app0.bin

Align 3.5C pins with CYD_PROJECT_GUIDE: TFT_BL=27, SGP30 SDA22/SCL21.

2026-10-25 10:53:33 +08:00

bootloader.bin

Align 3.5C pins with CYD_PROJECT_GUIDE: TFT_BL=27, SGP30 SDA22/SCL21.

2026-10-25 10:53:33 +08:00

firmware.bin

Align 3.5C pins with CYD_PROJECT_GUIDE: TFT_BL=27, SGP30 SDA22/SCL21.

2026-10-25 10:53:33 +08:00

flash.bat

Align 3.5C pins with CYD_PROJECT_GUIDE: TFT_BL=27, SGP30 SDA22/SCL21.

2026-10-25 10:53:33 +08:00

flash.ps1

Align 3.5C pins with CYD_PROJECT_GUIDE: TFT_BL=27, SGP30 SDA22/SCL21.

2026-10-25 10:53:33 +08:00

meta.json

Align 3.5C pins with CYD_PROJECT_GUIDE: TFT_BL=27, SGP30 SDA22/SCL21.

2026-10-25 10:53:33 +08:00

partitions.bin

Align 3.5C pins with CYD_PROJECT_GUIDE: TFT_BL=27, SGP30 SDA22/SCL21.

2026-10-25 10:53:33 +08:00

VERSION.txt

Align 3.5C pins with CYD_PROJECT_GUIDE: TFT_BL=27, SGP30 SDA22/SCL21.

2026-10-25 10:53:33 +08:00