dsx2016/ld2420test
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Restore 3.5 LD2420 wiring: OT1->GPIO21, RX->GPIO22.

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Keep TFT_BL=27; do not remap UART to GPIO4.

Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
DESKTOP-PUHFO60\dsx2016
2026-10-25 11:07:43 +08:00
parent 786f48ebd6
commit 14d5f9f68e
7 changed files with 19 additions and 19 deletions
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6
platformio.ini
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@@ -1,6 +1,6 @@
; CYD ESP32-2432S028R — LVGL LD2420 mmWave radar dashboard
; LD2420 OT1 -> GPIO22 (ESP RX); module RX -> GPIO27 (2.8 ESP TX) / GPIO4 (3.5 ESP TX)
; See ../CYD_PROJECT_GUIDE.md — 3.5 BL=27, GT911 INT=21 (not BL).
; 2.8: OT1->GPIO22 (ESP RX), RX->GPIO27 (ESP TX)
; 3.5: OT1->GPIO21 (ESP RX), RX->GPIO22 (ESP TX); BL=27
[platformio]
default_envs = cyd_28r
@@ -68,7 +68,7 @@ build_flags =
; Optional 3.5" CYD ESP32-3248S035C (ST7796 + GT911 capacitive). Default remains cyd_28r.
; Build: pio run -e cyd_35r
; Keep TOUCH_CS=-1 — GPIO33 is GT911 SDA, not resistive touch CS.
; TFT_BL=GPIO27 (not 21 — 21 is GT911 INT). LD2420 ESP TX -> GPIO4 (27=BL).
; TFT_BL=GPIO27. LD2420: OT1->GPIO21, RX->GPIO22.
[env:cyd_35r]
lib_deps =
lvgl/lvgl@9.2.2