Fix 3.5" backlight to GPIO27 and document CYD board pitfalls.

Align cyd_35r with 3248S035C pinout (BL!=INT) and point to CYD_PROJECT_GUIDE.

Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
2026-10-25 10:38:23 +08:00
parent 0a58ed8a79
commit 71fde27f05
5 changed files with 217 additions and 26 deletions

View File

@@ -54,19 +54,27 @@ build_flags =
extra_scripts = pre:copy_lv_conf.py
; Optional 3.5" CYD ESP32-3248S035 (ST7796 resistive). Default remains [env:cyd].
; Optional 3.5" CYD ESP32-3248S035C (ST7796 + GT911 capacitive). Default [env:cyd].
; Build: pio run -e cyd_35r
; Keep TOUCH_CS=-1 — GPIO33 is GT911 SDA, not resistive touch CS.
; TFT_BL=GPIO27 (not 21 — 21 is GT911 INT). See ../CYD_PROJECT_GUIDE.md §1.1
[env:cyd_35r]
extends = env:cyd
build_unflags =
-DILI9341_2_DRIVER=1
-DTFT_WIDTH=240
-DTFT_HEIGHT=320
-DTFT_BL=21
-DLV_MEM_SIZE=49152
build_flags =
${env:cyd.build_flags}
-UILI9341_2_DRIVER
-DST7796_DRIVER=1
-UTFT_WIDTH
-UTFT_HEIGHT
-DTFT_WIDTH=320
-DTFT_HEIGHT=480
-UTFT_BL
-DTFT_BL=27
-DCYD_BOARD_3248S035=1
-DUSE_HSPI_PORT
-DSUPPORT_TRANSACTIONS
-DTFT_RGB_ORDER=TFT_BGR
-DLV_MEM_SIZE=32768