Align 3.5C pins with CYD_PROJECT_GUIDE: TFT_BL=27, SGP30 SDA22/SCL21.

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Leave 2.8 wiring unchanged; release GT911 INT after reset so SCL21 can share CN1.

Co-authored-by: Cursor <cursoragent@cursor.com>

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This commit is contained in:

DESKTOP-PUHFO60\dsx2016

2026-10-25 10:53:33 +08:00

parent 1b2fe27fd9

commit ee2ca3edfc

16 changed files with 487 additions and 92 deletions

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